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E2E1021-27-Y3
Semiconductor MSM65355
Semiconductor 8-Bit Microcontroller with A/D Converter (with LCD Driver)
This version: MSM65355 Jan. 1998 Previous version: Nov. 1996
GENERAL DESCRIPTION
The MSM65355 is a high-performance 8-bit microcontroller that employs OKI original nX-8/50 CPU core. The MSM65355 includes 16K bytes of program memory, 384 bytes of data memory, an LCD driver, an A/D converter and shift registers. Also available is the MSM65P355, which replace the on-chip program memory with one-time PROM.
FEATURES
* Operating range Operating voltage Operating temperature Operating frequency (dual clock) High speed side Low speed side Current consumption (Typ.) High speed side Low speed side * Minimum instruction execution time * CPU core * General memory space * Local memory space * LCD driver * I/O port Input-output port Input port Output port * Timers : : : : : : : : : : : 2.7 to 5.5V -20 to +70 C 0 to 10MHz (@ VDD = 5V 10%) 0 to 10MHz (@ VDD = 2.7 to 5.5V) 75kHz/32.768kHz (@ VDD = 2.7 to 5.5V) 5mA (@ 5MHz, VDD = 3V), 20mA (@ 10MHz, VDD=5V) 45mA (@ 32.768kHz, VDD = 3V) 4mA (@ VDD = 3V, stop mode) 400ns (@ 10MHz), 800ns (@ 5MHz) 8-bit CPU core nX-8/50 Internal 16K-byte program memory Internal 384-byte data memory + SFR 16 4 (1/4, 1/3, and 1/2 duties are selectable with software.) 5 ports 8 bits, 1 port 6 bits, 1 port 5 bits, 1 port 4 bits 1 port 8 bits, 1 port 1 bit 1 port 1 bit 8-bit auto-reload timer 4 (clock for PWM frequency setting, shift clock for shift register) 16-bit auto-reload timer 1 Watchdog timer 1 Watch timer counter 1 Time base counter 1 (14-bit) 4ch 8-bit duty, frequency 1Hz to 80kHz (@ 10MHz) 1, selectable at 1600Hz, 3200Hz and 6400Hz (@ 10MHz) Synchronous with auto-transfer function 1 Synchronous 2 1/18
: : : :
* Counters * PWM * Buzzer output * Serial port
: : : :
Semiconductor * A/D converter * External interrupts : :
MSM65355
8 ch, 8 bits 3, selectable for rising edge/falling edge/both edges. * External interrupt for a remote control input (with 8-bit capture) : 1, selectable for rising edge/falling edge/both edges, with a sampling circuit for noise prevention. With rising edge operating capture and falling edge capture. * Remote control circuit : Can receive at 75/32.768kHz. * Interrupt sources : 22 * Package: 100-pin plastic QFP (QFP100-P-1420-0.65-BK4) (Product name: MSM65355-GS-BK4) indicates the code number. * Others A 1/2 OSC clock, XT clock or a 4-times XT clock can be selected as the CPU clock. The time base counter can be selected to be 1/4n of the CPU clock (n=1 to 8). On-chip power-on reset circuit. The state during STOP (maintaining of either high impedance or previous state) can be set for each port. (The current consumption of a port in the high impedance setting is less than 1mA.) - All input-output ports can be set to be pull-up or open. (Ports 0, 1, 2, and 6 can be set to be pull-up or open for each bit.) - A/D accuracy (1.5LSB @VDD=4.5 to 5.5V)
2/18
Semiconductor
BLOCK DIAGRAM
XT XT OSC0 OSC1 RESET CLKOUT* HSTOP* XTOUT*
ROM (16K bytes) OSC. CONT. INST. DEC. GMAR ALU T/C IR PC
BUS CONT.
8-bit SHIFT-REG
SFTO2* SFTI2* SFTCK2*
CPU CORE
RAM (384 bytes)
VDD GND
TBC
WDT
PWM0* PWM1* PWM2* PWM3* BZ*
8-bit PWM x 4
BUZZER OUTPUT
16-bit TIMER x 1 AR BR PSW SP LMAR 8-bit TIMER x 4 8-bit SHIFT-REG (16-byte autotransfer function) 8-bit A/D C 8ch 8-bit SHIFT-REG
T2CK* T1OUT* T0CK* GATE* SFTO0* SFTI0* SFTCK0* SFTO1* SFTI1* SFTCK1* INT0* INT1* INT2*
I/O PORT
LCD DRIVER
WATCH TIMER
REMOTE CONTROL CIRCUIT
INTERRUPT CONT. REMOTE CONTROL CAPTURE
SEG15
COM4 SEG0
C2 C1 VDD3 VDD2 VDD1 COM1
AGND
AI0-7*
VRH
AVDD
P0
P1
P2
P3
P4
P5
P6
P7
P8
MSM65355
SAMPLING CIRCUIT
INTRMC*
3/18
*Secondary functions of each port.
Semiconductor
MSM65355
PIN CONFIGURATION (TOP VIEW)
100 C2 99 C1 98 VDD3 97 VDD2 96 VDD1 95 P6.7 94 P6.6 93 P6.5 92 P6.3 91 P6.3 90 P6.2 89 P6.1(TEST) 88 P6.0(IN) 87 RESET 86 P2.0/SFTCK0 85 P2.1/SFTI0 84 P2.2/SFTO0 83 P2.3/INT2 82 P2.4 81 XT
COM1 COM2 COM3 COM4 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 AGND P3.0/AI0 P3.1/AI1 P3.2/AI2 P3.3/AI3 P3.4/AI4 P3.5/AI5 P3.6/AI6 P3.7/AI7 VRH 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
XT GND OSC0 OSC1 P0.0/INT0 P0.1/HSTOP P0.2/T1OUT P0.3/T0CK P0.4/INT1/GATE P0.5/CLKOUT P0.6/T2CK P0.7/BZ VDD P1.0/PWM3 P1.1/PWM2 P1.2/OWM1 P1.3/PWM0 P1.4/INTRMC P1.5/SFTCK1 P1.6/SFTI1 P1.7/SFTO1 P7.7/SFTO2 P7.6/SFTI2 P7.5/SFTCK2 P7.4/XTOUT P7.3 P7.2 P7.1 P7.0 P4.0
AVDD P8.0 P8.1 P8.2 P8.3 P5.7 P5.6 P5.5 P5.4 P5.3 P5.2 P5.1 P5.0 P4.7 P4.6 P4.5 P4.4 P4.3 P4.2 P4.1
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100-Pin Plastic QFP
4/18
Semiconductor
MSM65355
PIN DESCRIPTIONS
Basic Function
Function Power Pin 68 79 31 21 30 96 97 98 99 Oscillator 100 78 77 Symbol Type VDD GND AVDD AGND VRH VDD1 VDD2 VDD3 C1 C2 OSC0 OSC1 - - - - - - - - - - I O Digital power supply (5V) Digital ground Analog power supply (5V) Analog ground Analog reference voltage LCD drive bias output LCD drive bias output LCD drive bias output Capacitor connecting pins for LCD drive bias generation Oscillator input pin: connects to a crystal oscillator (or ceramic resonator) or external clock. Oscillator output pin: connects to a crystal oscillator (or ceramic resonator). When an external clock is input to OSC0, leave OSC1 open. XT-side oscillator input pin: connects a crystal oscillator of 32.768kHz or 75kHz. XT-side oscillator output pin: connects a crystal oscillator of 32.768kHz or 75kHz. System reset input: when this pin goes low, the internal state of the chip is initialized and program execution restarts from address 0040H. The input is pulled up to VDD with an internal pull-up resistor. Description
80 81 Control 87
XT XT RESET
I O I
Ports
76 to 69 67 to 60 86 to 82 22 to 29 51 to 44 43 to 36
P0.0 to P0.7 P1.0 to P1.7 P2.0 to P2.4 P3.0 to P3.7 P4.0 to P4.7 P5.0 to P5.7
I/O 8-bit input-output port (port 0): input or output can be selected for each bit by the port 0 direction register (P0DIR). In addition to their input-output port functions, the pins of port 0 have secondary functions: see Secondary Function. I/O 8-bit input-output port (port 1): input or output can be selected for each bit by the port 1 direction register (P1DIR). In addition to their input or output port functions, the pins of port 1 have secondary functions: see Secondary Function. I/O 5-bit input-output port (port 2): input or output can be selected for each bit by the port 2 direction register (P2DIR). In addition to their input or output port functions, P2.0 and P2.1 have secondary functions: see Secondary Function. I 8-bit input port (port3): during A/D conversion, the pins of port 3 function as analog input channels.
I/O 8-bit input-output port (port 4).
I/O 8-bit input-output port (port 5): input or output can be selected for each bit by the port 5 direction register (P5DIR).
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Semiconductor Basic Function (Continued)
Function Ports Pin 88 89 Symbol Type P6.0 P6.1 (TEST) P6.2 to P6.7 P7.0 to P7.7 P8.0 to P8.3 COM1 to COM4 SEG0 to SEG15 I O 1-bit input port (port 6.0) Description
MSM65355
1-bit output port (port 6.1). After reset, this port is pulled up to 1. During reset, if this port is forcibly cleared to 0, this IC goes into test mode, disabling execution of the use program.
90 to 95 52 to 59 32 to 35 LCD Driver 1 to 4 5 to 20
I/O 6-bit input-output port (port6)
I/O 8-bit input-output port (port7): input or output can be selected for each bit by the port 7 direction register (P7DIR). In addition to their input or output port functions, P7.4 to P7.7 pins have secondary functions: see Secondary Function. I/O 8-bit input-output port (port8): Input or output can be selected for each bit by the port 8 direction register (P8DIR). O LCD common signal output pin
O
LCD segment signal output pin
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Semiconductor Secondary Function
Function External interrupt Pin 76 Symbol Type INT0 I Description
MSM65355
Secondary function of P0.0: input pin for external interrupt 0. The interrupt can be triggered by the rising edge, falling edge, or both edges. Secondary function of P0.4: input pin for external interrupt 1. The interrupt can be triggered by the rising edge, falling edge, or both rising and falling edges. Also used as a gate signal input pin for gating the counter of timer 0. Secondary function of P2.3: input pin for external interrupt 2. The interrupt can be triggered by the rising edge, falling edge, or both rising and falling edges. Secondary function of P0.1: input pin for hard stop mode. If this pin goes low while the HSTP bit in SBYCON is set to "1", the chip enters hard stop mode. In hard stop mode the clock stops and the CPU and on-chip peripheral functions shut down to conserve power. Secondary function of P0.3: external clock input pin for timer 0. Secondary function of P0.2: This pin outputs a waveform with twice the cycle of the overflow interval of timer 1. Secondary function of P0.6: external clock input pin for timer 2. Secondary function of P3.0 to P3.7: These pins function as analog input channel in A/D conversion. Secondary function of P1.3: PWM channel 0 output pin. Secondary function of P1.2: PWM channel 1 output pin. Secondary function of P1.1: PWM channel 2 output pin. Secondary function of P1.0: PWM channel 3 output pin. Secondary function of P0.5: clock output pin for 1/2 dividing or 1/4 dividing of OSCCLK or XTCLK. Secondary function of P7.4: XTCLK output pin. Secondary function of P0.7: buzzer output pin Secondary function of P1.4: remote control input pin.
72
INT1
I
83
INT2
I
Control
75
HSTOP
I
Timer 0 Timer 1 Timer 2 A/D Converter PWM
73 74 70 22 to 29 64 65 66 67
T0CK T1OUT T2CK AI0 to AI7 PWM0 PWM1 PWM2 PWM3 CLKOUT XTOUT BZ INTRMC
I O I I
O O O O O O O I
Clock Output
71 56
Buzzer Output Remote Control Input
69 63
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Semiconductor Secondary Function (Continued)
Function Shift Register Pin 84 85 86 Symbol Type SFTO0 SFTI0 SFTCK0 O I Description
MSM65355
Secondary function of P2.2: shift register 0 data output pin. Secondary function of P2.1: shift register 0 data input pin.
I/O Secondary function of P2.0: shift register 0 synchronizing clock input-output pin. In master mode: clock output In slave mode: clock input O I Secondary function of P1.7: shift register 1 data output pin. Secondary function of P1.6: shift register 1 data input pin.
60 61 62
SFTO1 SFTI1 SFTCK1
I/O Secondary function of P1.5: shift register 1 synchronizing clock input-output pin. In master mode: clock output In slave mode: clock input O I Secondary function of P7.7: shift register 2 data output pin. Secondary function of P7.6: shift register 2 data input pin.
59 58 57
SFTO2 SFTI2 SFTCK2
I/O Secondary function of P7.5: shift register 2 synchronizing clock input-output pin. In master mode: clock output In slave mode: clock input
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Semiconductor
MSM65355
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Output Voltage Power Dissipation Storage Temperature Symbol VDD VI VO PD TSTG Ta=25C, per package Ta=25C, per output -- Ta=25C Condition Rating -0.3 to +7.0 -0.3 to VDD+0.3 -0.3 to VDD+0.3 400 50 -55 to +150 mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Voltage Memory Hold Voltage Oscillation Operating Frequency*1 External Clock Operating Frequency Operating Temperature
*1
Symbol VDD VDDMH fOSC fXT
*2
Condition -- fOSC=0 Hz -- VDD=2.7 to 5.5 -- --
Range 2.7 to 5.5 2.0 to 5.5 1 to 10 32.768/75 0 to 10 -20 to +70
Unit V MHz kHz MHz C
fEXTCLK Top
*1 Depends on specifications for a crystal or ceramic resonator. *2 External clock cannot be used for XT pin.
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Semiconductor
MSM65355
ELECTRICAL CHARACTERISTICS
DC Characteristics 1 (VDD=4.5 to 5.5V)
Parameter "H" Input Voltage "H" Input Voltage "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 LCD Driving Bias Output Voltage
*3 *4 *3 *4 *1 *2
(GND=0V, Ta=-20 to +70C) Min. 2.4 0.75VDD -- 0.75VDD 0.75VDD -- -- 1.2 2.6 4.0 -- VDD1-0.4 VDD2-0.4 VDD3-0.4 -- -40 --
*7 *8 *9
Symbol VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 VDD1 VDD2 VDD3 V0 V1 V2 V3
*5 *6
Condition CPUCLK=1MHz CPUCLK=1MHz CPUCLK=1MHz IOH=-200mA IOH=-400mA IOL=1.6mA IOL=3.2mA VDD=5V C1, C2, C3=0.1mF VSEL=0 (5V mode) I=+10mA VDD1=1.4V, I=10mA VDD2=2.8V, I=10mA VDD3=4.2V, I=-10mA VI=VDD/0V VI=0V, VDD=5V f=1MHz, Ta=25C Stop mode CPUCLK=32kHz, halt mode CPUCLK=32kHz, no load CPUCLK=10MHz, halt mode CPUCLK=10MHz, no load
Typ. -- -- -- -- -- -- -- 1.4 2.8 4.2 -- -- -- -- -- -200 5 15 30 80 8 20
Max. -- -- 0.8 -- -- 0.4 0.4 -- -- -- 0.4 VDD1+0.4 VDD2+0.4 -- 10 -400 -- 30 60 160 16 50
Unit
V
Segment/Common Driving Output Voltage
Input Leakage Current "L" Input Current Input Capacitance
ILI2 IIL CI IDD1
mA pF mA mA mA mA mA
-- -- -- -- --
Operating Current Consumption VDD = 5V XT = 32kHz OSC = 10MHz
IDD2 IDD3 IDD4 IDD5
*1 *2 *3 *4 *5 *6 *7 *8 *9
Excluding OSC0 and RESET OSC0 and RESET Excluding P4 P4 Excluding RESET RESET No load, including hard stop mode When OSC clock is stopped and LCD is operating When OSC clock is stopped
10/18
Semiconductor DC Characteristics 2 (2.7V VDD < 4.5V)
Parameter "H" Input Voltage "H" Input Voltage "L" Input Voltage "H" Output Voltage 1 "H" Output Voltage 2 "L" Output Voltage 1 "L" Output Voltage 2 LCD Driving Bias Output Voltage
*3 *4 *3 *4 *1 *2
MSM65355
(GND=0V, Ta=-20 to +70C) Min. 0.3VDD+0.9
*10
Symbol VIH1 VIH2 VIL VOH1 VOH2 VOL1 VOL2 VDD1 VDD2 VDD3 V0
Condition CPUCLK=1MHz CPUCLK=1MHz CPUCLK=1MHz IOH=-10mA IOH=-20mA IOL=10mA IOL=20mA VDD=3V C1, C2, C3=0.1mF VSEL=0 (3V mode) I=+10mA VDD1=1.4V, I=10mA VDD2=2.8V, I=10mA VDD3=4.2V, I=-10mA VI=VDD/0V VI=0V, VDD=3V f=1MHz, Ta=25C Stop mode CPUCLK=32kHz, halt mode CPUCLK=32kHz, no load CPUCLK=5MHz, halt mode CPUCLK=5MHz, no load
*7 *8 *9
Typ. -- -- -- -- -- -- -- 1.4 2.8 4.2 -- -- -- -- -- -125 5 4 15 45 1.5 5
Max. -- -- 0.3VDD-0.1 -- -- 0.1 0.1 -- -- -- 0.4 VDD1+0.4 VDD2+0.4 -- 10 -250 -- 8 30 90 3 16
*11
Unit
0.6VDD+0.6 -- 0.75VDD 0.75VDD -- -- 1.2 2.6 4.0 -- VDD1-0.4 VDD2-0.4 VDD3-0.4 -- -40 -- -- -- -- -- --
V
Segment/Common Driving Output Voltage
V1 V2 V3
Input Leakage Current 1 *5 "L" Input Current Input Capacitance
*6
ILI2 IIL CI IDD1
mA pF mA mA mA mA mA
Operating Current Consumption VDD = 3V XT = 32kHz OSC = 5MHz
IDD2 IDD3 IDD4 IDD5
*1 Excluding OSC0 and RESET *2 OSC0 and RESET *3 Excluding P4 *4 P4 *5 Excluding RESET *6 RESET *7 No load, including hard stop mode *8 When OSC clock is stopped and LCD is operated *9 When OSC clock is stopped *10 More than 3.375V *11 Less than 0.8V
11/18
Semiconductor AC Characteristics * CPU control
MSM65355
(VDD=2.7 to 5.5V, GND=0V, Ta=-20 to +70C) Parameter RESET Pulse Width Symbol tRESW Condition -- Min. 20 Max. -- Unit ns
* Peripheral control 1
(VDD=2.7 to 5.5V, GND=0V, Ta=-20 to +70C) Parameter Clock Cycle Clock "L" Pulse Wedth EXI T0 T2 External Interrupt Pulse Width External Clock Pulse Width GATE Pulse Width External Clock Pulse Width Symbol tC tCLW tEXIW tT0CW tT0GW tT2CW -- Condition VDD=4.5 to 5.5V 2.7V VDD < 4.5V -- Min. 100 200 0.45tC 4CPUCLK 4CPUCLK 1 tT0CLK 4CPUCLK
*1 *1 *2 *1
Max. -- -- 0.55tC -- -- -- --
Unit
OSC
ns
*1 CPUCLK : Supply clock for CPU selected by SBYCON *2 tT0CLK : Timer 0 count clock cycle selected by T0CON
* Peripheral control 2
Parameter OSC Clock Cycle SFTCK Cycle SFTCK "L" Pulse Width SFTCK "H" Pulse Width SFT0-2 SFTO Setup Time SFTO Hold Time SFTI Setup Time SFTI Hold Time Symbol tC tSFC0-2 tSFCLW0-2 tSFCHW0-2 tSFOS0-2 tSFOH0-2 tSFIS0-2 tSFIH0-2 CL=100pF Condition VDD=4.5 to 5.5V
(VDD=2.7 to 5.5V, GND=0V, Ta=-20 to +70C) Min. 100 200 8CPUCLK* 4CPUCLK-20* 4CPUCLK-20* tSFCLW0-2-100 tSFCHW0-2-100 100 100 Max. -- -- -- -- -- -- -- -- -- ns Unit
2.7V VDD < 4.5V
* CPUCLK : Supply clock for CPU selected by SBYCON
12/18
Semiconductor * A/D Converter Characteristics 1
MSM65355
(VDD=AVDD=VRH=4.5 to 5.5V, GND=AGND=0V, Ta=-20 to +75C) Parameter Resolution Linearity Error Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time * Symbol n See the recommended circuit. EL ED EZS EFS ECT tCONV See the measuring circuit. fOSC=10 MHz Analog input source impedance RI 5kW -- -- -- -- -- -- -- -- -- -- -- 16 Condition Min. -- Typ. 8 Max. -- +1.5 -1.5 0.5 +1.5 -1.5 0.5 -- Unit bit LSB LSB LSB LSB LSB ms/CH
*
The conversion just after setting GO bit to "1" : 14.8ms/CH
* A/D Converter Characteristics 2
(VDD=AVDD=VRH, 2.7V VDD < 4.5V, GND=AGND=VRL=0V, Ta=-20 to +75C) Parameter Resolution Linearity Differential Linearity Error Zero Scale Error Full Scale Error Crosstalk Conversion Time * Symbol n See the recommended circuit. EL ED EZS EFS ECT tCONV See the measuring circuit. fOSC=5 MHz Analog input source impedance RI 5kW -- -- -- -- -- -- -- -- -- -- -- 32 Condition Min. -- Typ. 8 Max. -- +2 -2 1 +2 -2 1 -- Unit bit LSB LSB LSB LSB LSB ms/CH
*
The conversion just after setting GO bit to "1" : 29.6ms/CH
13/18
Semiconductor
MSM65355
Definition of Terms Resolution Recognizable minimum input analog value. This can be resolved into 28=256, that is, VRH 256 in 8 bits. Deviation between ideal conversion characteristics as an 8-bit A/D converter and actual conversion characteristics. (Quantization error not included.) Ideal conversion characteristics means a step, where voltage is divided between VRH and AGND into 256. Shows the smoothness of conversion characteristics. 1LSB= VRH 256 is ideal for analog input voltage width corresponding to change per 1 bit of digital output. The differential linearity error is the deviation between this ideal bit size and a bit size at arbitrary point in conversion range. Deviation between ideal conversion characteristics of transfer point for digital outputs "000H" to "001H" and actual conversion characteristics. Deviation between ideal conversion characteristics of transfer point for digital outputs "0FEH" to "0FFH" and actual conversion characteristics.
Linearity Error
Differential Linearity Error
Zero Scale Error
Full Scale Error
14/18
Semiconductor
MSM65355
Recommended circuit
VRH
AVDD
VDD VDD
MSM65355 -
+
+
RI
0.1 mF AI0-7
47mF
0V Analog Voltage Input AGND 0.1mF GND
RI (Analog input source impedance) 5kW
Crosstalk measuring circuit
-
+
5kW AI0 AI1 Crosstalk is defined as the difference of A/D conversion result between supplying the same voltage to AI0 to AI7 and supplying voltage shown in this left diagram.
Analog Voltage Input 0.1mF
AI7
VREF or AGND
15/18
Semiconductor * Timing diagram CPU control
1) RESET pulse width tRESW RESET
MSM65355
Peripheral control 1
tC OSC0 tCLW
1) EXI pulse width tEXIW INT0-2
2) T0 tT0CW T0CK tT0GW GATE
3) T2 tT2CW T2CK
16/18
Semiconductor Peripheral control 2
1) SFT0-2 tSFC tSFCLW SFTCK tSFCHW
MSM65355
tSFOS SFTO tSFIS SFTI
tSFOH
tSFIH
17/18
Semiconductor
MSM65355
PACKAGE DIMENSIONS
(Unit : mm)
QFP100-P-1420-0.65-BK4
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 1.54 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, SOJ, QFJ (PLCC), SHP and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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